View ICS950104_296260.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Integrated Circuit Systems, Inc.
ICS950104
Advance Information
Programmable System Clock Chip for PIIITM Processor
Recommended Application: SIS630ST style chipset Output Features: * 1 - CPU clocks @ 2.5V * 1 - Pair of differential CPU clocks @ 3.3V * 9 - SDRAM @ 3.3V * 7 - PCI @3.3V * 1 - 48MHz, @3.3V * 1 - 24/48MHz @ 3.3V * 3 - REF @3.3V, (selectable strength) through I2C Features: * Programmable ouput frequency * Programmable ouput rise/fall time * Programmable CPU, SDRAM, and PCI skew * Real time system reset output * Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage * Watchdog timer technology to reset system if over-clocking causes malfunction * Uses external 14.318MHz crystal Skew Specifications: * CPU - CPU: <250ps * PCI - PCI: <500ps * SDRAM - SDRAM: <250ps * CPU - SDRAM:<350ps * CPU - PCI: <3ns
Pin Configuration
CPUCLKC0 CPUCLKT0 VDDCPU GND AVDD X1 X2 **FS0/REF0 VDDREF **FS1/REF1 REF2 GND *FS2/PCICLK_F PCICLK0 PCICLK1 PCICLK2 GND VDDPCI PCICLK3 PCICLK4 PCICLK5 AVDD48 **MULTSEL/24_48MHz **FS3/48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND IREF GND CPUCLK VDDL SDATA SDRAM_STOP#* SDRAM0 SDRAM1 SDRAM2 SDRAM3 VDD GND SDRAM4 SDRAM5 SDRAM6 SDRAM7 GND VDD PCI_STOP#* CPU_STOP#* PD#/Vtt_PWRGD#* SCLK GND
48-Pin 300mil SSOP
Notes: REF0 can be 1X or 2X strength controlled by I2C. * Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down of 120K to GND
Functionality Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
3
REF(2:0)
CPU DIVDER
Stop
CPUCLKT0 CPUCLKC0 CPUCLK
SDATA SCLK FS(3:0) PD# PCI_STOP# CPU_STOP# MODE MULTSEL
Control Logic
SDRAM DIVDER
Stop
10
SDRAM (9:0)
PCI DIVDER
Stop
6
PCICLK (5:0) PCICLK_F
Config. Reg.
CPU (MHz) 66.6 100.0 150.0 133.3 66.8 100.0 100.0 133.3 66.8 97.0 70.0 95.0 95.0 112.0 97.0 96.2
ICS950104
SDRAM (MHz) 100.0 100.0 100.0 100.0 133.6 133.3 150.0 133.3 66.8 97.0 105.0 95.0 126.7 112.0 129.3 96.2
PCICLK (MHz) 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.3 35.0 31.7 31.7 37.3 32.2 32.1
950104 Rev - 09/11/01 Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS950104
Advance Information
Pin Descriptions
PIN NUMBER 1 PIN NAME CPUCLKC0 TYPE OUT DESCRIPTION "Complementary" clocks of differential pair CPU outputs. These clocks are 180 out of phase with SDRAM clocks. These open drain outputs need an external 1.5V pull-up. "True" clocks of differential pair CPU outputs. These clocks are in phase with SDRAM clocks. These open drain outputs need an external 1.5V pull-up. Power supply pins, nominal 3.3V Ground pins Analog power supply for 3.3V Crystal input,nominally 14.318MHz. Crystal output, nominally 14.318MHz. Frequency select pin. 14.318 MHz reference clock. Frequency select pin. 14.318 MHz reference clock. 14.318 MHz reference clock. Frequency select pin. Free running PCICLK not stoped by PCI_STOP# PCI clock outputs. 3.3V LVTTL input for selecting the current multiplier for CPU outputs.
2 3, 9, 18, 30, 37 4, 12, 17, 25, 31, 36, 46, 48 5, 22 6 7 8 10 11 13 21, 20, 19, 16, 15, 14 23 24 26
CPUCLKT0 VDD GND AVDD X1 X2 FS0 REF0 FS1 REF1 REF2
2, 3
OUT PWR PWR PWR IN OUT IN OUT IN OUT OUT IN OUT OUT IN OUT IN OUT IN IN
2, 3
FS2 PCICLK_F PCICLK(5:0) MULTSEL 24_48MHz FS3 48MHz SCLK
1 2, 3 2, 3
1, 3
Selectable 48 or 24MHz output
Frequency select pin. 48MHz output clock Clock input of I C input, 5V tolerant input Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. This pin will be activiated when This 3.3V LVTTL input is a level sensitive strobe used to determine when FS and MULTISEL0 inputs are valid and are ready to be sampled (active low) This asynchronous input halts CPU, SDRAM, and AGP clocks at logic "0" level when driven low, the stop selection can be programmed through I C. Stops all PCICLKsbesides the PCICLK_F clocks at logic 0 level, when input low SDRAM clock outputs. Stops all SDRAMs besides the SDRAM_F clocks at logic 0 level, when input low Data input for I C serial input, 5V tolerant input Power supply pins, nominal 2.5V 2.5V CPU clock
2 2 2
PD# 27
VttPWRGD#
IN
28 29 32, 33, 34, 35, 38, 39, 40, 41 42 43 44 45 47
CPU_STOP# PCI_STOP#
1
IN IN OUT
1
1
SDRAM ( 7:0 )
SDRAM_STOP#
SDATA VDDL CPUCLK
IN IN PWR OUT
I REF
OUT
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current.
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 3: Internal Pull-down resistor of 120K to GND on indicated inputs.
Third party brands and names are the property of their respective owners.
2
ICS950104
Advance Information
General Description
The ICS950104 is a main clock synthesizer chip for PIII based systems with ALI 1651 style chipset. This provides all clocks required for such a system. The ICS950104 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
MULTISEL0
Board Target Trace/Term Z 50 ohms 50 ohms
Reference R, Iref = VDD/(3*Rr) Rr = 221 1%, Iref = 5.00mA Rr = 475 1%, Iref = 2.32mA
Output Current Ioh = 4* I REF Ioh = 6* I REF
Voh @ Z
0 1
1.0V @ 50 0.7V @ 50
Third party brands and names are the property of their respective owners.
3
ICS950104
Advance Information General I2C serial interface information for the ICS950104 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). * Controller (host) will need to acknowledge each byte * Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK
ACK ACK ACK ACK ACK ACK ACK
How to Read:
Controlle r (Host) Start Bit Address D3 (H ) ICS (Sla ve /Re ce ive r)
ICS (Slave/Receiver)
ACK
A CK Byte Count Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 ACK If 7H has been written to B8 ACK Byte 7
Byte 18 ACK Byte 19 ACK Byte 20 ACK Stop Bit
If 12H has been written to B8 ACK If 13H has been written to B8 ACK If 14H has been written to B8 ACK Stop Bit Byte18 Byte 19 Byte 20
*See notes on the following page.
Third party brands and names are the property of their respective owners.
4
ICS950104
Advance Information Brief I2C registers description for ICS950104 Programmable System Frequency Generator
Register Name Functionality & Frequency Select Register Output Control Registers Byte 0 Description Output frequency, hardware / I C frequency select, spread spectrum & output enable control register. Active / inactive output control registers/latch inputs read back. Byte 11 bit[7:4] is ICS vendor id - 1001. Other bits in this register designate device revision ID of this part. Writing to this register will configure byte count and how many byte will be read back. Do not write 00 H to this byte. Writing to this register will configure the number of seconds for the watchdog timer to reset. Watchdog enable, watchdog status and programmable 'safe' frequency' can be configured in this register. This bit select whether the output frequency is control by hardware/byte 0 configurations or byte 11&12 programming. These registers control the dividers ratio into the phase detector and thus control the VCO output frequency. These registers control the spread percentage amount. Increment or decrement the group skew amount as compared to the initial skew. These registers will control the output rise and fall time.
2
PWD Default See individual byte description See individual byte description See individual byte description
1-6
Vendor ID & Revision ID Registers
7
Byte Count Read Back Register
8
08 H
Watchdog Timer Count Register
9
10 H
Watchdog Control Registers 10 Bit [6:0]
000,0000
VCO Control Selection Bit
10 Bit [7]
0
VCO Frequency Control Registers Spread Spectrum Control Registers Group Skews Control Registers Output Rise/Fall Time Select Registers
11-12
Depended on hardware/byte 0 configuration Depended on hardware/byte 0 configuration See individual byte description See individual byte description
13-14
15-16 17-20
Notes:
1. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to byte 8. When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written but not 15, neither byte 14 or 15 will load into the receiver. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only Block-Writes from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
2. 3. 4. 5. 6.
7.
Third party brands and names are the property of their respective owners.
5
ICS950104
Advance Information
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default = 0)
Description Bit7 Bit2 Bit6 Bit5 Bit4 CPU SDRAM 0 0 0 0 0 66.6 100.0 0 0 0 0 1 100.0 100.0 0 0 0 1 0 150.0 100.0 0 0 0 1 1 133.3 100.0 0 0 1 0 0 66.8 133.6 0 0 1 0 1 100.0 133.3 0 0 1 1 0 100.0 150.0 0 0 1 1 1 133.3 133.3 0 1 0 0 0 66.8 66.8 0 1 0 0 1 97.0 97.0 0 1 0 1 0 70.0 105.0 0 1 0 1 1 95.0 95.0 0 1 1 0 0 95.0 126.7 0 1 1 0 1 112.0 112.0 0 1 1 1 0 97.0 129.3 0 1 1 1 1 96.2 96.2 Bit 7, 2, Bit 6:4 1 0 0 0 0 66.8 100.2 1 0 0 0 1 100.2 100.2 1 0 0 1 0 166.0 110.7 1 0 0 1 1 100.2 133.6 1 0 1 0 0 75.0 100.0 1 0 1 0 1 83.3 125.0 1 0 1 1 0 105.0 140.0 1 0 1 1 1 133.6 133.6 1 1 0 0 0 110.3 147.0 1 1 0 0 1 115.0 153.3 1 1 0 1 0 120.0 120.0 1 1 0 1 1 138.0 138.0 1 1 1 0 0 140.0 140.0 1 1 1 0 1 145.0 145.0 1 1 1 1 0 147.5 147.5 1 1 1 1 1 160.0 160.0 0 - Frequency is selected by hardware select, Latched Inputs Bit 3 1 - Frequency is selected by Bit 7, 2, 6:4 0 - Normal Bit 1 1 - Spread Spectrum Enabled 0 - Running Bit 0 1- Tristate all outputs Bit PWD PCI 33.3 33.3 37.5 33.3 33.4 33.3 37.5 33.3 33.4 32.3 35.0 31.7 31.7 37.3 32.3 32.1 33.4 33.4 27.7 33.4 37.5 31.3 35.0 33.4 36.8 38.3 30.0 34.5 35.0 36.3 36.9 26.7 SS 0 to-0.5% 0 to-0.5% 0.25% 0 to-0.5% 0 to-0.5% 0 to-0.5% 0.25% 0 to-0.5% 0.25% 0 to-0.5% 0.25% 0.25% 0.25% 0.25% 0 to-0.5% 0 to-0.5% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25% 0.25%
00010 Note1
0 1 0
Note: PWD = Power-Up Default Note1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3. The I2C readback for Bits 7, 2, 6:4 indicate the revision code. I2C is a trademark of Philips Corporation
Third party brands and names are the property of their respective owners.
6
ICS950104
Advance Information
Byte 1: CPU, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 11 10 24 8 8, 10, 11 1, 2 PWD X 1 1 1 1 1 1 1 FS3# REF2 REF1 48MHz REF0 REF(2:0) 1X, 2X d e fa u l t = 1 = 1 X ( R e s e r ve d ) CPUCLKT/C0 DESCRIPTION
Byte 2: PCI, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 21 20 19 16 15 14 13 PWD X 1 1 1 1 1 1 1 DESCRIPTION (Reserved) PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 PCICLK_F
Byte 3: SDRAM, Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 33 32 45 23 PWD X X X 1 1 1 1 1 FS0# FS1# FS2# SDRAM6 SDRAM7 (Reserved) CPUCLK 24_48MHz DESCRIPTION
Byte 4: Reserved , Active/Inactive Register (1= enable, 0 = disable)
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 41 40 39 38 35 34 PWD 1 1 1 1 1 1 1 1 DESCRIPTION (Reserved) (Reserved) SDRAM0 SDRAM1 SDRAM2 SDRAM3 SDRAM4 SDRAM5
Byte 5: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN# PWD
1 1 1 1 1 1 0 0
DESCRIPTION
(Reserved) 24_48MHz select: 0=48MHz, 1=24MHz (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Notes:
PIN# -
PWD 0 0 0 0 0 1 1 1
DESCRIPTION R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
7
ICS950104
Advance Information
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 1 X X X X X
Description Vendor ID Vendor ID Vendor ID Revision ID Revision ID Revision ID Revision ID Revision ID
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 1 0 0 0
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Byte 9: Watchdog Timer Count Register
Byte 10: VCO Control Selection Bit & Watchdog Timer Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 1 0 0 0 0
Description The decimal representation of these 8 bits correspond to how many 290ms the watchdog timer will wait before it goes to alarm mode and reset the frequency to the safe setting. Default at power up is 16X 290ms = 4.64 seconds.
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 0 0 0 0 0 0 0 0
Description 0=Hw/B0 freq / 1=B11 & 12 freq WD Enable 0=disable / 1=enable WD Status 0=normal / 1=alarm WD Safe Frequency, Byte 0 bit 2 WD Safe Frequency, FS3 WD Safe Frequency, FS2 WD Safe Frequency, FS1 WD Safe Frequency, FS0
Note: FS values in bit (0:4) will correspond to Byte 0 FS values. Default safe frequency is same as 00000 entry in byte0.
Byte 11: VCO Frequency Control Register
Byte 12: VCO Frequency Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit0 REF Divider Bit6 REF Divider Bit5 REF Divider Bit4 REF Divider Bit3 REF Divider Bit2 REF Divider Bit1 REF Divider Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description VCO Divider Bit8 VCO Divider Bit7 VCO Divider Bit6 VCO Divider Bit5 VCO Divider Bit4 VCO Divider Bit3 VCO Divider Bit2 VCO Divider Bit1
Note: The decimal representation of these 7 bits (Byte 11 (6:0)) + 2 is equal to the REF divider value .
Notes: 1. PWD = Power on Default
Note: The decimal representation of these 9 bits (Byte 12 bit (7:0) & Byte 11 bit (7) ) + 8 is equal to the VCO divider value. For example if VCO divider value of 36 is desired, user need to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit & byte 11 bit 7.
Third party brands and names are the property of their respective owners.
8
ICS950104
Advance Information
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Spread Spectrum Bit7 Spread Spectrum Bit6 Spread Spectrum Bit5 Spread Spectrum Bit4 Spread Spectrum Bit3 Spread Spectrum Bit2 Spread Spectrum Bit1 Spread Spectrum Bit0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Spread Spectrum Bit12 Spread Spectrum Bit11 Spread Spectrum Bit10 Spread Spectrum Bi 9 Spread Spectrum Bit8
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Note: Please utilize software utility provided by ICS Application Engineering to configure spread spectrum. Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 1 1 1 1 1 1 1
Description (Reserved) CPUCLK Skew Control (Reserved) SDRAM (7:0) Skew Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD Description 0 0 PCICLK (5:0, F) Skew Control 0 0 0 1 (Reserved) 0 0
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description (Reserved) CPUCLK Slew Rate Control PCICLK_F Slew Rate Control PCICLK (5:0) Slew Rate Control
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD 1 0 1 0 1 0 1 0
Description (Reserved) SDRAM (7:0) Slew Control (Reserved) 48MHz Slew Rate Control
Notes: 1. PWD = Power on Default 2. The power on default for byte 13-20 depends on the harware (latch inputs FS(4:0)) or I2C (Byte 0 bit (1:7)) setting. Be sure to read back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass. 3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
Third party brands and names are the property of their respective owners.
9
ICS950104
Advance Information
Byte 19: Reserved Register
Byte 20: Reserved Register
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWD X X X X X X X X
Description Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Note: Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not affect device performance or functinality.
VCO Programming Constrains VCO Frequency ...................... 150MHz to 500MHz VCO Divider Range ................ 8 to 519 REF Divider Range ................. 2 to 129 Phase Detector Stability .......... 0.3536 to 1.4142 Useful Formula VCO Frequency = 14.31818 x VCO/REF divider value Phase Detector Stabiliy = 14.038 x (VCO divider value)-0.5 To program the VCO frequency for over-clocking. 0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming. 1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by writing to byte 0, or using initial hardware power up frequency. 2. Write 0001, 1001 (19H) to byte 8 for readback of 21 bytes (byte 0-20). 3. Read back byte 11-20 and copy values in these registers. 4. Re-initialize the write sequence. 5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values. 6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate. 7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed again, user only needs to write to byte 11 and 12 unless the system is to reboot. Note: 1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship. 2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly. 3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow. Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz). 4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO frequency. 5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See Application note for software support.
Third party brands and names are the property of their respective owners.
10
ICS950104
Advance Information
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . . 0C to +70C Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70 C; Supply Voltage VDD = 3.3V, VDDL = 2.5 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Input frequency Input Capacitance1 Clk Stabilization 1
1
SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP66 IDD3.3OP100 Fi CIN CINX TSTAB
CONDITIONS
MIN 2 VSS-0.3 -5 -200
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66MHz CL = 0 pF; Select @ 100MHz VDD = 3.3 V; Logic Inputs X1 & X2 pins From VDD = 3.3 V to 1% target Freq.
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 77 100 mA MHz pF pF ms
12 27
16 5 45 3
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
11
ICS950104
Advance Information
Electrical Characteristics - CPUCLKT/C
TA = 0 - 70 C; VDD = 3.3 V +/-5%; (unles s otherwis e s tated) PARAMETER Current Source Output Im pedance Output High Voltage Output High Current Ris e Tim e 1 Differential Cros s over Voltage 1 Duty Cycle 1 Skew 1, CPU to CPU Jitter, Cycle-to-cycle 1 SYMBOL ZO VOH IOH tr VX dt tsk tjcyc-cyc VO = VX VR = 475W +1%; IREF = 2.32m A; IOH = 6*IREF VOL = 20% , VOH = 80% Note 3 VT = 50% VT = 50% VT = VX 175 45 45 50 51 CONDITIONS MIN 3000 0.71 -13.92 1.2 700 55 55 100 150 TYP MAX UNITS V mA ps % % ps ps
Notes : 1 - Guaranteed by des ign, not 100% tes ted in production.
Electrical Characteristics - CPUCLK
T A = 0 - 70 C; V DD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; C L = 20 pF (unless otherwise stated) PARAM ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter, Cycle-to-cycle Jitter, One Sigma
1
SYM BOL VOH2 B VOL2 B IOH2 B IOL2B t r2 B t f2 B
1 1
CONDITIONS IOH = -12.0 mA IOL = 12 mA VOH = 1.7 V VOL = 0.7 V VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
M IN 2
TYP
M AX 0.4 -19
19 1.6 1.6 45 55 250 250 150
UNITS V V mA mA ns ns % ps ps ps
d t2 B 1 t sk 2 B
1 1
t jcy c-cy c2 B t j1 s 2B 1
VT = 1.25 V VT = 1.25 V
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
12
ICS950104
Advance Information
Electrical Characteristics - PCICLK
T A = 0 - 70C; V DD = 3.3 V +/-5%; C L = 10-30 pF (unless otherwise stated) PARAM ETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYM BOL VOH1 VOL1 IOH1 IOL1 t r1 1 t f1
1 1
CONDITIONS IOH = -1 mA IOL = 1 mA VOH@ M IN = 1.0 V, VOH@ M AX = 3.135 V VOL@ M IN = 1.95 V, VOL@ M AX= 0.4 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
M IN 2.4 -33 30 0.5 0.5 45
TYP
M AX 0.55 -33 38 2 2 55 175 500
UNITS V V mA mA ns ns % ps ps
d t1
ts k 1 1 t jcy c-cyc 1
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 30 pF (unless otherwise stated) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Propagation Delay
1 1
SYMBOL VOH3 VOL3 IOH3 IOL3 Tr3 Dt3
1
CONDITIONS IOH = -28 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
41
MAX UNITS V 0.4 V -54 mA mA 2 2 ns ns % ps ns
Tf3 1
1
45
55 250 5
Tsk1 Tprop
Guarenteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
13
ICS950104
Advance Information
Electrical Characteristics - 24MHz, 48MHz, REF
TA = 0 - 70 C; VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5%; CL = 20 pF (unless otherwise stated)
PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time
1 1 1 1
SYMBOL VOH5 VOL5 IOH5 IOL5 tr5 tf5 dt5 tj1s5 tjabs5
CONDITIONS IOH = -16 mA IOL = 9 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 2.4
TYP
16
MAX UNITS V 0.4 V -22 mA mA 2 2 ns ns % ns ns
Duty Cycle
45 -1
55 0.5 1
Jitter, One Sigma Jitter, Absolute
1
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
14
ICS950104
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
15
ICS950104
Advance Information
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94252. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS94252 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
CPUCLK (Internal)
PCICLK_F (Internal) PCICLK_F (Free-running) CPU_STOP#
PCI_STOP#
PCICLK
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94252 device.) 2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized inside the ICS94252. 3. All other clocks continue to run undisturbed. 4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
16
ICS950104
Advance Information
PD# Timing Diagram
The power down selection is used to put the part into a very low power state without turning off the power to the part. PD# is an asynchronous active low input. This signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. Internal clocks are not running after the device is put in power down. When PD# is active low all clocks need to be driven to a low value and held prior to turning off the VCOs and crystal. The power up latency needs to be less than 3 mS. The power down latency should be as short as possible but conforming to the sequence requirements shown below. PCI_STOP# and CPU_STOP# are considered to be don't cares during the power down operations. The REF and 48MHz clocks are expected to be stopped in the LOW state as soon as possible. Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one clock cycle to complete.
PD#
CPUCLK
PCICLK VCO Crystal
Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94252 device). 2. As shown, the outputs Stop Low on the next falling edge after PD# goes low. 3. PD# is an asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. 4. The shaded sections on the VCO and the Crystal signals indicate an active clock. 5. Diagrams shown with respect to 133MHz. Similar operation when CPU is 100MHz.
Third party brands and names are the property of their respective owners.
17
ICS950104
Advance Information
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS94252. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
INTERNAL CPUCLK PCICLK CPU_STOP# PD# (High)
CPUCLK PCI_STOP# (High)
Notes: 1. All timing is referenced to the internal CPU clock. 2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPU clocks inside the ICS94252. 3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
18
ICS950104
Advance Information
N
c
L
SYMBOL
INDEX AREA E1 E
12 D h x 45
a
A A1
A A1 b c D E E1 e h L N
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950104yFT
Example:
ICS XXXX y F - T
Designation for tape and reel packaging Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type Prefix ICS = Standard Device
Third party brands and names are the property of their respective owners.
19
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.

▲Up To Search▲

Price & Availability of ICS950104

	To Download ICS950104 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .